SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs0 pages

SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 05 — 12 January 2009
Product data sheet
1. General description
The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and
RXRDYn signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specic user requirements. An internal loopback capability allows
on-board diagnostics. Independent programmable baud rate generators are provided to
select transmit and receive baud rates.
The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages.
2. Features
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2 channel UART
5 V, 3.3 V and 2.5 V operation
5 V tolerant on input only pins1
Industrial temperature range
Pin and functionally compatible to 16C2450 and software compatible with INS8250,
SC16C550
Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V
16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
16-byte receive FIFO with error ags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive FIFO interrupt trigger levels
Software selectable baud rate generator
Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break)
Transmit, Receive, Line Status and Data Set interrupts independently controlled
For data bus pins D7 to D0, see Table 23 “Limiting values”.