Turbo PMAC CPU and memory Configurations0 pages

Turbo PMAC Application Notes

Turbo PMAC controllers can be provided with several different CPU and memory configurations. The user specifies the desired configuration by ordering one of the Opt 5xx CPU options. The x immediately following the 5 is a letter specifying the processor type, each with different speed and internal memory capacity. The second x is a number specifying the amount of memory external to the processor. Processor Types Turbo PMAC controllers use digital signal processors (DSPs) from Freescale (formerly Motorola) of the DSP563xx family. >

Harvard Architecture Memory

The Freescale (formerly Motorola) DSP563xx CPUs used in Turbo PMAC controllers utilize a Harvard architecture, with separate memory banks for data and instructions. This architecture is more efficient, but less flexible, than the more common von Neumann architecture used in most general-purpose computers. In a given application, a given bank of physical memory cannot be switched between the two uses. Each CPU/memory configuration of the Turbo PMAC makes a specific division between the two banks of memory, and this division cannot be changed by the user. >

Instruction (Program) Memory

The instruction memory bank contains the actual machine-code instructions executed by the processor. These instructions must have been compiled or assembled from the source code before loading into the Turbo PMAC memory. This bank is called the P (program) memory bank, and is very seldom accessed directly by a user. Each instruction register is a 24-bit word. There are four possible sets of instructions in the P memory bank: 1. Firmware: This code is written and loaded by Delta Tau, and must be present for the Turbo PMAC to operate.2. Compiled PLCs: The user can load up to 32 compiled PLC programs into Turbo PMACs P memory. The download routines of the Executive program and PCOMM library automatically compile code designated for compiled PLCs and load it into the appropriate section of Turbo PMAC P memory. 3. User-Written Servo: The user can load a custom servo algorithm either an Open Servo algorithm compiled with the Pro Executive program, or assembled with a cross-assembler provided by Freescale/Motorola. 4. User-Written Phase: The user can load a custom phase (commutation) algorithm, assembled with a cross-assembler provided by Freescale/Motorola. >

Data Memory

The data memory bank contains the data registers on which the instructions act. Note that interpreted programs Җ both motion programs and uncompiled PLC programs are data, because they do not contain the actual machine-code instructions that the processor directly executes. The data memory bank is organized as a set of 48-bit double words, each split into an X register and a Y register. In addition to the user֒s interpreted programs, the data memory bank contains fixed-use registers, and any defined data buffers that the user creates, such as compensation tables, lookahead buffers, and data-
gathering buffers. >
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